1. Field of the Invention
The present invention relates to integrated circuits, and, more particularly, to built-in, self-test processing in an integrated circuit.
2. Description of the Related Art
As integrated circuit technology advances, the scale of integration (“density”) for the various circuit elements has increased to provide greater functionality from a single semiconductor chip. Circuit elements are predominantly memory elements, sometimes referred to as regular structure (RS) elements, and random logic (RL) elements. RS elements may include RAM, ROM, CAM, FIFO, and embedded core elements, while RL elements comprise digital logic such as AND, XOR, and state machines.
Increasing the density of the various circuit elements also increases the difficulty in testing the operation of the circuit elements by external testing equipment. The increase in testing difficulty is, in-part because of the difficulty in obtaining test-points within the embedded architecture for each of the RS and RL elements. In addition, the increased density increases the time that is required to test the entire chip. Consequently, chip designers are increasingly using “Design for Testability” in their circuit architectures to include built-in self-test (BIST) capability to allow the chip to “test itself” (BISTed test functionality).
However, BISTed test functionality within, for example, Very Large Scale Integrated (VLSI) circuits is complex when implemented. Typically, an interface is provided within the circuit to coordinate communication between an external test controller and various RS and RL elements within the circuit to initiate and schedule BISTed test functions efficiently. U.S. Pat. No. 5,570,374 to Yau et al. (“Yau”), which is incorporated in its entirety herein by reference, describes a network for BIST functionality. In Yau, a controller (termed an “SBRIC”) coordinates operation of one or more BISTed elements (RS and RL elements having BIST functionality, termed RSB elements and RLB elements, respectively). In addition, Yau describes a plurality of controllers for RS elements, SBRIC_RSs, coupled in a daisy-chain configuration. The first SBRIC_RS in the chain serves to initiate testing of a first group of RSB elements, the second SBRIC_RS in the chain serves to initiate testing of a second group of RSB elements, and so on through the chain. Each SBRIC_RS in the chain is responsive to a signal generated by the previous SBRIC_RS in the chain to begin testing, and, thus, groups of RSB elements are tested in sequence. Testing in sequence may be required when tests by one SBRIC_RS require data generated during testing of a prior SBRIC_RS.
To increase BIST functionality, U.S. Pat. No. 5,978,947 to Kim et al. (“Kim”), which is incorporated in its entirety herein by reference, describes a token passing network for BIST functionality. In Kim, a Universal BIST Scheduler (UBS) is employed to initiate processing of a group of SBRICs arranged in a matrix. As in Yau, Kim's SBRIC_RSs each coordinate operation of one or more BISTed RS elements (an SBRIC_RL coordinates operation for one or more BISTed RL elements). The UBS schedules operations of multiple SBRIC_RSs concurrently to utilize continuous processing. Arranging the group of SBRICs into a matrix allows the UBS to initiate processing by an SBRIC based upon the SBRIC's position in the matrix to ensure data generated by one SBRIC is available for use by another SBRIC. A token is employed and transferred between SBRICs in the matrix as processing is completed.
In addition, Kim includes a multi-test stage design also employing the scheduling capability of the UBS. During a first test stage, a BISTed test function is implemented for a given RSB element and the results are reflected in test data (termed test signature or signature bits) associated with the RSB element. After the first test stage and before the second test stage, a waiting period for retention testing begins. Retention testing identifies retention faults in the RSB element or the loss of a data value stored in a memory location (cell or word). Retention faults occur from leakage of one or more bits previously written to a memory location. Retention testing requires a waiting period to allow any leakage, if present, to occur. During the second test stage, memory locations of each RSB element are read to test whether, after the waiting period, binary values resulting from BIST testing during the first test stage were retained. In addition, the binary values are toggled to form a complement pattern. After another waiting period, retention testing during the third test stage verifies that the complement pattern is retained. Scheduling by the USB allows for separate processing to occur between test stages and retention testing.
The relatively large size of integrated circuits results in longer interconnect routing lengths between RSB and RSL elements, or groups of RSB and RSL elements. Interconnect routing provides paths for signals, including test signals, between various locations within the integrated circuit. These longer interconnect routing lengths cause increased signal delay and clock skew, especially with global chip signals, such as control signals, in relatively long signal paths throughout the chip.